1. Field of the Invention
The present invention is related to processing systems and processors, and more specifically to techniques for handling queuing of requests to memory devices that reduce the impact of high-latency memory operations such as refresh.
2. Description of Related Art
Present day memory controllers include substantial queuing mechanisms that facilitate forward queuing of memory requests. A command queue is used to store incoming requests, which are then processed and placed in a re-order queue, that permits issuing of memory operations that can be processed with overlap, such as accesses to different devices, or sub-arrays that can be accessed independently. By re-ordering operations, the memory bandwidth can be substantially improved over that of memories in which operations must be performed sequentially.
Memory controllers, in addition to providing access to the memory devices and using queues to improve throughput, must also queue accesses while portions of the memory are unavailable for access. Dynamic random-access memories (DRAMS) typically require substantial internally-timed or externally-timed refresh intervals, and memories in general such as static random-access memories (SRAMS) and DRAMS have other housekeeping logic that performs non-memory access housekeeping operations such as bus calibration operations, making some memory regions inaccessible for significant periods during which memory accesses must be queued.
It would therefore be desirable to provide a memory controller and a method of managaing memory operations that improve performance of memory accesses, in particular when high-latency housekeeping operations such as DRAM refresh or bus calibration must be performed.